Advanced Computer Architecture Chapter 7.15
Multiple caches… and
trouble
Suppose
processor 1 loads memory location x
x is fetched from main memory and allocated
into processor 1’s cache(s) as
wellFirst-level cache
x
CPU
second-level cache
x
First-level cache
x
CPU
second-level cache
x
First-level cache
CPU
second-level cache
Interconnection network
Main
memory
x
Processor 0
Processor 1
Processor 2